Fabrication of fets

Details Fabrication of fets Fabrication of fets

H - Electricity

01

L

356/149

H01L 21/02 (2006.01) H01L 21/285 (2006.01) H01L 21/336 (2006.01) H01L 29/417 (2006.01) H01L 29/45 (2006.01)

Patent

CA 1203322

- 13 - FABRICATION OF FETs Abstract A method of fabricating FETs to reduce parasitics. Contact is made to the source and drain regions through a polycrystalline silicon runner which is aligned with the edge of the gate electrode. This is accomplished by providing a layer such as palladium over the gate electrode and depositing the polycrystalline silicon layer over the device. The polycrystalline silicon and palladium form a silicide which is then selectively etched leaving the remaining polycrystalline silicon aligned with the gate.

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