Fabrication of interlayer conductive paths in integrated...

Details Fabrication of interlayer conductive paths in integrated... Fabrication of interlayer conductive paths in integrated...

H - Electricity

01

L

356/136

H01L 21/44 (2006.01) H01L 21/768 (2006.01) H01L 23/482 (2006.01) H01L 23/532 (2006.01)

Patent

CA 1286795

Abstract A method of producing interlayer conductive paths having substantially planar top surfaces in a multilayer integrated circuit structure, comprising the steps of forming elements of either a conductive or semiconductive material as a lower layer, depositing an insulative layer on top of the lower layer elements, implanting ions into one or more selected regions of the insulative layer, forming at least one upper conductor over the selected regions and sintering the integrated circuit structure sufficient to render the selected regions conductive. The invention also embraces an integrated circuit structures with interlayer conductive paths made in accordance with this method.

569061

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