H - Electricity – 01 – L
Patent
H - Electricity
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H01L 21/20 (2006.01) H01L 21/18 (2006.01) H01L 21/265 (2006.01) H01L 21/321 (2006.01) H01L 21/335 (2006.01) H01L 21/337 (2006.01) H01L 21/338 (2006.01) H01L 25/065 (2006.01)
Patent
CA 2066002
Disclosed is a new method suitable for making highly integrated quantum wire arrays, quantum dot arrays in a single crystal compound semiconductor and FETs of less than 0.1 micron gate length. This makes it possible to construct a high-performance electronic device with high speed and low power consumption, using a combination of low-temperature-growth molecular beam epitaxy (LTG-MBE) and focused ion beam (FIB) implantation. The compound semiconductor (GaAs) epitaxial layers, which are made by LTG-MBE, are used as targets of Ga FIB implantation to make Ga wire or dot arrays. Precipitation of arsenic microcrystals, which are initially embedded in a single crystal GaAs layer and act as Schottky barriers, are typically observed in an LTG GaAs layer. A thermal annealing process, after implantation, changes the arsenic microcrystals to GaAs crystals if the arsenic microcrystals are in the region in which the Ga ions are implanted. A wire-like shape free of As microcrystals then acts as a quantum wire for electrons or holes whereas a dot-like shape free of As microcrystals acts as a quantum dot. The co-existence of Ga ions and dopant ions, which provides conductivity type carriers opposite to the conductivity type of the majority carriers of a channel region of an FET, provides the fabrication of very narrow junction gate region for any FET.
Fukuzawa Tadashi
Munekata Hiro
International Business Machines Corporation
Saunders Raymond H.
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