Fabrication process for aligned and stacked cmos devices

Details Fabrication process for aligned and stacked cmos devices Fabrication process for aligned and stacked cmos devices

H - Electricity

01

L

356/149, 148/3,

H01L 21/82 (2006.01) H01L 21/225 (2006.01) H01L 21/31 (2006.01) H01L 21/312 (2006.01)

Patent

CA 1295534

A FABRICATION PROCESS FOR ALIGNED AND STACKED CMOS DEVICES Abstract of the Disclosure A process for fabricating aligned, stacked CMOS devices. Following the formation of the lower FET device, conformal undoped and doped oxide layers are formed thereover so that the level of the upper surface of the common gate electrode is above the doped oxide as formed in the source and drain regions of the lower FET device. A planarizing photoresist is then deposited and etched in conjunction with the oxide to the upper surface of the gate electrode. The exposed gate electrode is covered with a gate oxide layer, and a polycrystalline silicon layer for recrystallization to an upper FET device. Updiffusion from the residuals of doped oxide then creates an upper FET device with source and drain regions aligned to the gate oxide thereof and the underlying common gate electrode.

526926

Affiliated with

Also associated with

Rating

Fabrication process for aligned and stacked cmos devices does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Fabrication process for aligned and stacked cmos devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fabrication process for aligned and stacked cmos devices will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1312528