Facilitation of register updates in an out-of-order processor

Details Facilitation of register updates in an out-of-order processor Facilitation of register updates in an out-of-order processor

G - Physics

06

F

G06F 9/30 (2006.01) G06F 9/312 (2006.01) G06F 9/318 (2006.01) G06F 9/38 (2006.01)

Patent

CA 2317080

A processor including a register, an execution unit, a temporary result buffer, and a commit function circuit. The register includes at least one register bit and may include one or more sticky bits. The execution unit is suitable for executing a set of computer instructions. The temporary result buffer is configured to receive, from the execution unit, register bit modification information provided by the instructions. The temporary result buffer is suitable for storing the modification information in set/clear pairs of bits corresponding to respective register bits of the register. The commit function circuit is configured to receive the set/clear pairs of bits from the temporary result buffer when the instruction is committed. The commit function circuit is suitable for generating an updated bit in response to receiving the set/clear pairs of bits. The updated bit is then committed to the corresponding register bit of the register.

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