Fail safe architecture for a computer system

Details Fail safe architecture for a computer system Fail safe architecture for a computer system

G - Physics

06

F

354/224, 354/225

G06F 11/00 (2006.01) G06F 11/08 (2006.01)

Patent

CA 1272292

ABSTRACT The fail safe architecture for a computer system includes a read only memory (ROM) self-check module, a random access memory (RAM) self-check module and operation code instructions (op code) self-check module which are actuated periodically by a non-maskable interrupt (NMI) to a microprocessor. The microprocessor then suspends the current applications routine being executed. If the self-check module detects a failure, the microprocessor enters a fail safe trap routine which initially resynchronizes the operation of the microprocessor and then delays the generation of a critical timing pulse (fail safe trigger) with a series of "jump to yourself" steps. The fail safe trigger signal activates a device which sends a fail safe square wave to a narrow bandwidth, digital, band-pass filter. If the fail safe square wave signal is not supplied to the filter during a prescribed period of time, a set of transistor switches, interposed between the computer system power supply and the voltage regulator for the computer system, is not actuated and power is cut off to the computer system. Otherwise, if the fail safe signal is received within the prescribed window of time, switches are actuated to couple the power supply to the computer system.

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