Fail safe digital timer

H - Electricity – 03 – K

Patent

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Details

328/188, 342/19.

H03K 17/28 (2006.01) F23N 5/20 (2006.01) F23N 5/24 (2006.01) G04F 1/00 (2006.01) G06F 11/16 (2006.01)

Patent

CA 1159913

ABSTRACT OF THE DISCLOSURE A fail safe digital timer is provided by having a pair of similar counters counting the output of a single clock means. The clock means provides clock pulses and complimentary clock pulses to the two counters and the outputs of the counters are compared. If the two counters are properly operating the compar- ison will provide a continuous stream of pulses at a frequency equal to the frequency of the clock means for the timer. The failure of any of the components in the system cause the output of the comparator means to either become a constant logic 1 or a constant logic 0.

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