Failure information processing in automatic memory tester

Details Failure information processing in automatic memory tester Failure information processing in automatic memory tester

G - Physics

11

C

354/224, 324/58.

G11C 29/00 (2006.01) G11C 29/56 (2006.01) G01R 31/3193 (2006.01) G06F 11/00 (2006.01) G06F 11/277 (2006.01) G06F 11/32 (2006.01)

Patent

CA 1281775

Abstract of the Disclosure Automatic memory tester apparatus for processing failure information of a memory under test (MUT) including a high speed pattern generator for providing digital test patterns to the MUT for storage of data at MUT addresses in the MUT, a failure processor for comparing outputs from the MUT with expected outputs to obtain failure information, a fail map random access memory (RAM) having fail map addresses corresponding to the MUT addresses and connected to receive the failure information and store it at corresponding fail map addresses, the fail map addresses including bits to address individual bits of multibit words, and an address generator means for randomly addressing and reading individual bits of the multibit words to provide a serial bit output.

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