Fast learn digital adaptive equalizer

Details Fast learn digital adaptive equalizer Fast learn digital adaptive equalizer

H - Electricity

03

H

328/0.2

H03H 17/02 (2006.01) G06F 7/00 (2006.01) H04L 25/03 (2006.01)

Patent

CA 1157917

Abstract of the Disclosure An automatic adaptive equalizer operative on a test pattern including a carrier-only period, clock-only period and a single test impulse. The equalizer employs a transversal filter under control of a microprocessor. Samples of in-phase and quadrature phase components of the received impulse response are cross correlated and autocorrelated to form elements of a complex matrix equation describing the optimum equalizer tap settings. The microprocessor performs a special iterative operation utilizing elements of this equation to rapidly and exactly calculate the optimum initial settings for the tap constants. The clock-only portion of the test pattern is analyzed to accurately set a sampling clock to properly sample the received impulse so that the matrix formation can be carried out during the duration of the received impulse. Initial equalization can be achieved in a time on the order of 30 milliseconds at a data rate of 9600 bits per second.

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