Fast recovery bias circuit

Details Fast recovery bias circuit Fast recovery bias circuit

H - Electricity

04

L

325/122

H04L 7/10 (2006.01) G08B 3/10 (2006.01) H04L 25/06 (2006.01) H04L 7/04 (2006.01)

Patent

CA 1221420

FAST RECOVERY BIAS CIRCUIT Abstract A programmable bias circuit for use with a data limiter circuit is described. The limiter and bias circuit are coupled to a portable data receiver which is adapted to communicate in a coded system. Frequency disparities between a transmitted word sync signal and the portable data terminal local oscillator signal will cause a DC offset voltage in the received data signal. The programmable bias circuit is controlled by a decoder within the portable data terminal. If the terminal is in an idle state, the programmable bias circuit will be set to rapidly follow offset voltage shifts until a transmitted word sync signal has been detected. After word sync has been detected, a slower, more stable time constant circuit is programmably activated for the duration of the digital data message. The fast time constant circuit is activated at the end of the received data signal.

468580

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