Fast sample and hold circuit configuration

Details Fast sample and hold circuit configuration Fast sample and hold circuit configuration

H - Electricity

03

K

328/171

H03K 5/153 (2006.01) G11C 27/02 (2006.01) H03F 1/30 (2006.01)

Patent

CA 2015006

Abstract of the Disclosure: A circuit configuration includes a symmetrically constructed sample and hold amplifier. A first switchable level shifter has an input in the form of a first signal input terminal for receiving a given signal, and an output being connected to the sample and hold amplifier for supplying a differential output signal. A second switchable level shifter has an input in the form of a second signal input terminal for receiving a signal complementary to the given signal, and an output being connected to the sample and hold amplifier for supplying a differential output signal. The input and output signals of each of the switchable level shifters having a different constant direct voltage difference as a function of the switching state of the level shifters.

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