Fast summing circuit

Details Fast summing circuit Fast summing circuit

G - Physics

06

F

354/197

G06F 7/50 (2006.01) G06F 7/52 (2006.01)

Patent

CA 1283981

Abstract of the Disclosure: A summing circuit (20) is for summing up zeroth through n-th input data signals A(O) to A(n) to produce a sum signal S consisting of zeroth through m-th output bits s(O) to s(m) where n represents a first predetermined natural number and m represents a second predetermined natural number which is not less than the first predetermined natural number. A preprocessing circuit (22) preprocesses the zeroth through the n-th input data signals A(O) to A(n) into a preprocessed signal which is (n + 1) bits long. A logic circuit (24) carries out a logical operation on the preprocessed signal to produce the sum signal S. For example, each of the zeroth through the n-th input data signals A(O) to A(n) is given by an equation. Image where a(d) represents a d-th coefficient having one to logic zero and one values, k represents a predetermined integer which is not less than zero, and A represents a common coefficient having the logic zero value. Each of the zeroth through the n-th input data signals A(O) to A(n) may be given by another equation: Image where p(d)'s represent zeroth through n-th discrete integers.

569400

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