Fast two-level dynamic address translation method and means

Details Fast two-level dynamic address translation method and means Fast two-level dynamic address translation method and means

G - Physics

06

F

354/239

G06F 12/10 (2006.01) G06F 12/14 (2006.01)

Patent

CA 1229424

ABSTRACT OF THE DISCLOSURE The disclosure provides a unique high-speed hardware arrangement for generating double-level address translations in combination with a translation look-aside buffer (TLB) structure that can store and lookup intermediate translations during a double-level translation. The hardware proceeds to the completion of a double-level translation without having to backup its operation, although an intermediate TLB miss is encountered, without danger of CPU deadlock occurring. The hardware arrangement also performs all single-level address translations required by the system.

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