G - Physics – 11 – C
Patent
G - Physics
11
C
352/82.2
G11C 5/00 (2006.01) G11C 7/00 (2006.01) G11C 11/412 (2006.01)
Patent
CA 1234629
A Fast Writing Circuit for a Soft Error Protected Storage Cell Abstract A fast writing circuit is disclosed for a soft error protected storage cell, such as a latch. The protected latch has a first input/output node and a second input/output node which are respectively connected to a charging source. The latch is connected to a first binary state input device which is enabled by a write-enable input, the first node being selectively charged during a write interval when the write-enable input is on, to represent a stored, first binary logic state for the latch. The soft error protection circuit includes an insulated gate, field effect capacitor having a diffusion electrode connected to the second node and having a gate electrode, for selectively loading the second node with an additional capacitance when its gate is biased with respect to the diffusion electrode. The soft error protection circuit further includes an inverter circuit having an input connected to the second node and an output for applying a capacitance enhancing bias to the gate electrode of the capacitor, for capacitively loading the second node. The fast writing circuit disclosed herein has an insulated sate field effect transistor disabling device having its source connected to ground potential, its drain connected to the gate of the capacitor and its gate corrected to the write-enable input, for removing the bias on the gate of the capacitor in response to the write-enable input, thereby minimizing the capacitive load on the second node during the write interval. In this manner, the soft error protected latch can be written into at a faster rate than has been previously possible.
498314
International Business Machines Corporation
Saunders Raymond H.
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