Fault detection arrangement for a digital conferencing system

Details Fault detection arrangement for a digital conferencing system Fault detection arrangement for a digital conferencing system

H - Electricity

04

Q

344/1, 354/227

H04Q 1/20 (2006.01) G06F 11/10 (2006.01) H04M 3/56 (2006.01)

Patent

CA 1232660

- 51 - FAULT DETECTION ARRANGEMENT FOR A DIGITAL CONFERENCING SYSTEM Abstract The disclosure relates to error/fault detection in signal processing systems such as those employed in a time division multiplex conferencer. The digital message samples (of the conferees) and the accompanying parity bits are delivered to a signal processor e.g., a binary arithmetic adder. The adder sums the message samples and this sum is coupled to a first parity tree, which in response thereto generates a first parity bit. The carries generated by the summing operation are coupled to a second parity tree along with the message parity bits and the second parity tree generates a second parity bit therefrom. The first and second parity bits are compared and if they differ a fault exists. Corrective action is taken immediately--the faulty conference "leg" is removed from the conference connection without affecting the remaining legs in the conference or any other conference.

479734

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