Fault insertion method, boundary scan cells, and integrated...

Details Fault insertion method, boundary scan cells, and integrated... Fault insertion method, boundary scan cells, and integrated...

G - Physics

01

R

G01R 31/26 (2006.01) G01R 31/3185 (2006.01) G01R 35/00 (2006.01)

Patent

CA 2286473

A number of fault injection circuits and corresponding methods for injecting correlated, uncorrelated, non-persistent and persistent faults at the primary outputs of boundary scan cells are disclosed. Fault data is loaded in the boundary scan cell update latch of all boundary scan cells at which a fault is to be injected. The fault injection circuits generate a fault inject signal which is applied to the control input of the standard cell output selector, an active signal causing the content of the update latch to be applied to the cell primary output. In embodiments for injecting correlated, non-persistent faults, the data loaded into the update latch serves as both the fault data to be injected and also as a fault flag indicating whether the data is to be injected at the output of the cell and a fault type signals) is applied to indicate the type of fault to be injected. In embodiment, for injecting uncorrelated (different faults at each site) and/or persistent faults (which persist after structural tests) , the fault flag is stored in a fault flag latch or register which is arranged in parallel with the boundary scan cell update latch in such a manner that the fault data and fault flag data can be independently loaded into the update latch and fault flag latches, respectively, from the standard boundary scan cell shift register using a standard shift operation in which the boundary scan cell serial inputs and serial outputs are connected in series between the Test Access Port Test Data Input and Test Data Output. In embodiments for injecting persistent faults, logic is provided to prevent the data from being changed while the cells are in fault injection mode. In order to provide for scan testing of the fault injection circuitry, the boundary scan cell shift and update latches and the fault flag latch (if employed) are provided with hold capability so that the contents of these elements can be controlled and their input captured in accordance with standard scan testing techniques.

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