Fault testing a clock distribution network

Details Fault testing a clock distribution network Fault testing a clock distribution network

G - Physics

01

R

324/58.1

G01R 31/28 (2006.01) G01R 31/30 (2006.01) G06F 11/273 (2006.01) G06F 1/04 (2006.01) G06F 11/22 (2006.01)

Patent

CA 1208699

Abstract Fault Testing A Clock Distribution Network A method and apparatus for fault testing a clock distribution network which provides a plurality of clock signal lines to the logic networks which comprise a data processor. The fault testing apparatus includes a decoder for selecting one of the clock signal lines to be tested, and a test latch which is clocked by the selected clock signal line. The selected clock signal line is tested by setting the test latch to a first logic value (e.g., binary ZERO) and maintaining a second logic value (e.g., binary ONE) at the test latch input. If the second logic value is stored in the test latch when the clock distribution network is inhibited, then a stuck-on fault is indicated for the selected clock signal line. If the second logic value fails to be stored in the test latch when the clock distribution network is enabled, then a stuck-off fault is indicated for the selected clock signal line. Each clock signal line in the clock distribution network may be tested in this manner.

462899

Affiliated with

Also associated with

Rating

Fault testing a clock distribution network does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Fault testing a clock distribution network, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fault testing a clock distribution network will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1265916