Fault tolerant bubble memory with a single major loop having...

Details Fault tolerant bubble memory with a single major loop having... Fault tolerant bubble memory with a single major loop having...

G - Physics

11

C

352/37.2

G11C 11/14 (2006.01) G11C 19/08 (2006.01) G11C 29/00 (2006.01)

Patent

CA 1113608

ABSTRACT In a field access type bubble memory system using a major loop minor loop organization, additional redundant minor loops are included in each memory device so that defective minor loops may be disregarded and the memory retain its nominal capacity. Thus, the total number of minor loops is in excess of the nominal capacity. A stationary register is formed integrally with the major loop by coupling bubble idlers directly to the major loop bubble propagation path. The stationary register has as many register positions as the total number of minor loops coupled to the major loop. An appropriate binary code identifies in the appropriate register location the corresponding minor loop which is defective, includ- ing nominally defective minor loops, if necessary, so that a number of minor loops equal to the nominal capacity of the memory are identified as good. Each time the memory is accessed, the contents of the stationary register are accessed, nondestructively, and read into and combined with the contents of the major loop on an every other one basis. Appropriate logic identifies which minor loop is to receive data and those minor loops from which data can be read. A single conductor can be used to control access from both the stationary register and the minor loops to the major loop or separate conductors may be used for the stationary register and the minor loops.

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