G - Physics – 06 – F
Patent
G - Physics
06
F
354/222
G06F 11/16 (2006.01) G06F 1/12 (2006.01) G06F 1/30 (2006.01) G06F 11/07 (2006.01) G06F 11/14 (2006.01) G06F 11/18 (2006.01) G06F 11/20 (2006.01) G06F 11/10 (2006.01) G06F 11/22 (2006.01) G06F 11/273 (2006.01)
Patent
CA 2032067
FAULT-TOLERANT COMPUTER SYSTEM WITH ONLINE REINTEGRATION AND SHUTDOWN/RESTART ABSTRACT: A computer system in a fault-tolerant configuration employs multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. The system detects faults in the CPUs and memory modules, and places a faulty unit of offline while continuing to operate using the good units. The faulty unit can be replaced and reintegrated into the system without shutdown. The computer system employs a power supply system including a battery backup so that upon AC power failure the system can execute an orderly shutdown, saving state to disk. A restart procedure restores the state existing at the time of power failure if the AC power has been restored by the time the shutdown is completed. The system employs a pseudo-filesystem to dynamically manage the hardware components. A directory which appears as a standard, hierarchical directory in this filesystem contains a file for each component; each file maps to either a hardware component or a software module. The pseudo-filesystem hierarchy is determined during system initialization and is automatically updated whenever the software or hardware configuration changes. The pseudo-filesystem, called /config filesystem herein, is implemented as a Unix filesystem in the Unix filesystem switch. The multiple CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses. I/O devices are accessed through a pair of identical (redundant) I/O processors, but only one is designated to actively control a given device; in case of failure of one I/O processor, however, an I/O device can be accessed by the other one without system shutdown.
Aldridge Dave
Banton Randall G.
Bereiter Tom
Cutts Richard W. Jr.
Debacker Kenneth C.
Aldridge Dave
Banton Randall G.
Ben David Administrator Of The Estate Of Donald C. Westbrook Deceased
Bereiter Tom
Cutts Richard W. Jr.
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