Fault tolerant least recently used algorithm logic

G - Physics – 06 – F

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354/224

G06F 7/00 (2006.01) G06F 11/00 (2006.01) G06F 12/12 (2006.01)

Patent

CA 1053804

FAULT TOLERANT LEAST RECENTLY USED ALGORITHM LOGIC Abstract Binary logic is added to the binary logic normally utilized for the purpose of generating and decoding binary code combinations which reflect the order of use of a number of units, utilized in sequence, to thereby indicate the unit least recently used (LRU). Disclosed is the utilization of six binary bits which are updated in accordance with a sequence of use of four units to thereby indicate the least recently used one of the four units. In accordance with known LRU techniques, there are 24 valid binary bit combinations that reflect the sequence of use of the four units. The provision of 6 binary bits in the LRU code are capable of assuming 64 different permutations, therefore 40 combinations of binary bits are considered invalid when utilizing the LRU code. The present invention utilizes certain of the invalid binary bit combinations to identify units that have been removed from further use because of a fault condition, and which code continues to identify the sequence of use of those units which have not been eliminated from further use. The code chosen to identify a faulty unit and the sequence of use of the remaining units is fault tolerant in that additional errors in the coding mechanism can be tolerated, and ignored, while maintaining the ability to identify faulty units and sequence of use of the remaining units.

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