Fault tolerant memory

Details Fault tolerant memory Fault tolerant memory

G - Physics

06

F

354/237, 352/40.

G06F 11/10 (2006.01) G06F 11/00 (2006.01) G11C 8/08 (2006.01)

Patent

CA 1238715

FAULT TOLERANT MEMORY Abstract of the Disclosure A memory array architecture configured in one form with multiple subarrays addressable by row lines, bank select lines and column select lines, arranged so that no two data word bit positions having a common row line also share common bank select lines. The addition of isolation between the row lines and the row bus combined with the shifting or jogging of the bank select lines in adjacent subarrays ensures that a short circuit or open circuit in a row line no longer effects multiple bits in a common word. The ability to control the effects of manufacturing defects so that they commonly effect no more than a single bit position within a word makes feasible the use of error correction coding techniques within for example integrated circuit ROM type memories.

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