Fault tolerant smart card

Details Fault tolerant smart card Fault tolerant smart card

G - Physics

07

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354/222, 352/82

G07B 17/02 (2006.01) G06F 11/07 (2006.01) G06F 11/16 (2006.01) G06F 11/267 (2006.01) G06K 19/073 (2006.01) G07B 17/00 (2006.01) G07F 7/10 (2006.01) G06F 11/10 (2006.01) G06F 11/20 (2006.01)

Patent

CA 1315408

ABSTRACT OF THE DISCLOSURE A fault tolerant smart card is provided having primary functional units including a standard ISO interface, a first microcontroller, a clock, and main memory. Secondary functional units including a secondary microcontroller, secondary memory with bit checking capability and an alternate battery power source are also provided. A microcontroller error detector is connected to both microcontrollers. Should a discrepancy between microcontrollers occur known test patterns are run on the second microcontroller to determine which microcontroller is faulty. A private access port provides alternate access to information stored in the fault tolerant smart card. Registers for funds remaining, error condition and access account are also provided.

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