Fet bias circuit

Details Fet bias circuit Fet bias circuit

G - Physics

05

F

G05F 1/46 (2006.01) H03F 1/30 (2006.01)

Patent

CA 2335220

A circuit for biasing a Field Effect Transistor (FET) is provided. The FET has a gate, a drain, and a source and the circuit comprises a current limiting resistor having a first end and a second end, the first end being connected to the gate; and a closed-loop control circuit connected to the second end, applying and controlling DC voltage to the second end, so that a gate bias voltage that is applied to the gate becomes equal to a reference voltage of a predetermined DC voltage.

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