Fet capacitance driver logic circuit

H - Electricity – 03 – K

Patent

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328/128

H03K 19/017 (2006.01) H03K 19/00 (2006.01)

Patent

CA 1296074

ABSTRACT An improved FET capacitance driver logic circuit having an inverter feedback stage 22 connected from output to input of output FET 23 to allow the output FET to have a large capacitance charging current surge followed by a reduced conduction thereafter.

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