H - Electricity – 01 – L
Patent
H - Electricity
01
L
356/171, 356/74
H01L 29/78 (2006.01) H01L 21/28 (2006.01) H01L 21/336 (2006.01) H01L 29/04 (2006.01) H01L 29/34 (2006.01) H01L 29/423 (2006.01)
Patent
CA 1049157
FET DEVICE WITH REDUCED OVERLAP CAPACITANCE AND METHOD OF MANUFACTURE ABSTRACT A metal gate transistor is fabricated to have reduced gate overlap of source/drain regions and increased oxide thickness over the diffused regions whereby parasitic capacitance is reduced and switching speed is increased. The method comprises the steps of (1) selecting an appro- priate insulating thickness over a semiconductor substrate, (2) forming source/drain diffused regions in the substrate through openings in the insulating layer at appropriate diffusion temperatures, (3) selecting an appropriate drive- in and regrowth temperature whereby the insulating layer thickness over the diffused region is greater than that over the non-diffused region and out diffusion of the diffused regions is minimized, (4) etching the region between the source/drain to form a gate area and (5) growing a prescribed gate insulation thickness for a metal gate whereby the gate insulation overlap of the diffused region and the thickness of the gate insulation overlap of the diffused region reduce the parasitic capacitance and increase the switching speed of the resulting metal gate transistor relative to prior art tran- sistors.
254958
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