Fet memory cell structure and process

Details Fet memory cell structure and process Fet memory cell structure and process

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Patent

CA 1155972

FET Memory Cell Structure and Process Abstract A dense, vertical MOS FET memory cell has a high charge storage capacitance per unit area of substrate surface. The charge storage capacitor structure is formed within a well etched in the silicon semicon- ductor substrate by a combination of reactive ion etching and a self-limiting wet etch. FI 9-79-083

379798

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