H - Electricity – 01 – L
Patent
H - Electricity
01
L
356/149
H01L 21/22 (2006.01) H01L 21/28 (2006.01) H01L 21/31 (2006.01) H01L 21/336 (2006.01) H01L 21/82 (2006.01) H01L 21/8242 (2006.01) H01L 27/088 (2006.01) H01L 27/108 (2006.01) H01L 29/78 (2006.01)
Patent
CA 1079866
FET ONE-DEVICE MEMORY CELLS WITH TWO LAYERS OF POLYCRYSTALLINE SILICON Abstract of the Disclosure Fabricating an integrated circuit array of FET one-device memory cells which includes providing a semi- semiconductive substrate of a first conductive type; delineating field insulation regions; delineating polycrystalline silicon gate regions employing an oxidation barrier masking layer; introducing active impurities of a second and opposite con- ductive type into predetermined regions of the substrate to provide doped bit lines (FET drains), connection regions (FET sources), and lower conductive electrodes of the storage capacitors; next delineating upper poycrystalline silicon electrodes of the storage capacitors; growing silicon dioxide insulation over all portions of the structure except over the FET gate regions which are protected by the oxidation barrier masking layer; removing the oxidation barrier masking layer over the FET gates with an etchant; delineating contact holes to polycrystalline silicon capacitor electrodes and to FET sources and drains in circuits peripheral to the array of memory cells; and delineating the metallic-type high-conduc- tivity electrical interconnection word line pattern.
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