Fet read only memory with charge level sense circuitry and...

Details Fet read only memory with charge level sense circuitry and... Fet read only memory with charge level sense circuitry and...

G - Physics

11

C

352/82.3

G11C 11/40 (2006.01) G11C 17/00 (2006.01)

Patent

CA 1044371

READ ONLY MEMORY ABSTRACT An FET read only memory array having bit locations arranged in rows and columns utilizes a dynamic array and static sensing. A dynamic first address selects the gate line of a selected column and a second address selects the source line or lines to select one or more bits within the selected column. The presence or absence of a gate at a selected bit location determines whether a first or second logic level is present at the sense or drain line serving the bit location. An additional column of FET bit positions each with a gate has the gate line activated toward the conclusion of the cycle to provide a path to ground for the elimina- tion of any charge on a sense line in preparation for the next succeeding cycle. The sensed output from a selected bit location is latched until reset.

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