Fibonacci p-code parallel adder

Details Fibonacci p-code parallel adder Fibonacci p-code parallel adder

G - Physics

06

F

354/204

G06F 7/50 (2006.01)

Patent

CA 1127313

FIBONACCI p-CODE PARALLEL ADDER Abstract of the Disclosure A Fibonacci p-code parallel adder comprising an gauged register and anaddend register having their outputs coupled to the inputs of an end-of-addition detector and a monitoring unit and to the data inputs of a logic unit which comprises rewrite AND gates. The latter have their inputs coupled to the complement and true outputs respectively of the augend and addend registers so as to provide for analyzing the con- dition of the flip-flops of the registers, and have their outputs coupled to the set inputs of the bit positions of the augend register and, via a delay unit 7 to the reset inputs of the bit position of the addend register, which provides for transfer of a 1 from the ith bit position of the addend register to the ith bit position of the augend register containing a 0. A Fibonacci p-code minimizing unit has its inputs coupled to the outputs of the augend and addend registers, and has its iutputs coupled to the normalize signal input of the augend register. This allows for the reduction of the codeword con- tained in the augend register to the minimal form, the codeword containted in the addend register being taken into consideration.

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