H - Electricity – 01 – L
Patent
H - Electricity
01
L
H01L 29/812 (2006.01) H02G 1/02 (2006.01)
Patent
CA 2058465
Abstract of the Disclosure This invention aims at providing an high output FET having a planar type-gate structure suitable for integration, and a structure that suppresses long gate effect. A heavily doped thin channel layer 13 is formed on a semiconductor substrate 11, and a cap layer including a doped layer 15 is formed on the channel layer 13. A thickness and a dopant concentration of the doped layer 15 are so set that the doped layer 15 per se is depleted hy a surface depletion region resulting from an interface level of the semiconductor substrate surface, and the surface depletion region does not widen to the channel layer 13. Consequently no long gate effect takes place on the side where a gate bias is lower.
Kuwata Nobuhiro
Marks & Clerk
Sumitomo Electric Industries Ltd.
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