Field effect transistor

Details Field effect transistor Field effect transistor

H - Electricity

01

L

H01L 29/772 (2006.01) H01L 21/285 (2006.01) H01L 21/335 (2006.01) H01L 29/15 (2006.01) H01L 29/205 (2006.01) H01L 29/778 (2006.01)

Patent

CA 2231206

On an iron doped semi-insulating InP substrate, a first buffer layer of undoped In0.52Al0.48As, a second buffer layer in a super lattice structure of undoped In0.52Al0.48As and undoped Al0.25Ga0.75As, a third buffer layer of undoped In0.52Al0.48As, a channel layer of undoped In0.53Ga0.47As, a spacer layer of undoped In0.52Al0.48As, a delta dope layer of silicon and a Schottky layer of undoped In0.52Al0.48As are successively stacked. On the Schottky layer, a cap layer in a recessed structure is formed. On the cap layer, a source electrode and a drain electrode are formed, with a gate electrode formed in a recessed area of the cap layer.

Sur un substrat de semi-conducteur InP semi-isolé dopé au fer, on empile successivement une première couche tampon d'In0,52Al0,48As non dopé, une seconde couche tampon dans une structure de type super réseau d'In0,52Al0,48As non dopé et d'Al0,25Ga0,75As non dopé, une troisième couche tampon d'In0,52Al0,48As non dopé, une couche canal d'In0,53Ga0,47As non dopé, une couche d'espacement d'In0,52Al0,48As non dopé, une couche à dopage delta de silicium et une couche de Schottky d'In0,52Al0,48As non dopé. Sur la couche de Schottky, on forme une couche de recouvrement dans une structure encastrée. Sur la couche de recouvrement, une source et un drain sont formés, de même qu'une grille dans la zone encastrée de la couche de recouvrement.

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