Field effect transistor

Details Field effect transistor Field effect transistor

H - Electricity

01

L

H01L 29/812 (2006.01) H01L 29/10 (2006.01) H01L 29/80 (2006.01)

Patent

CA 2067048

Abstract of the Disclosure According to the invention, an FET includes an epitaxially grown n-type GaInAs channel layer, first and second undoped GaInAs layers formed to sandwich the channel layer, a buffer layer formed on a GaAs substrate to be in contact with one side of the first layer, and a cap layer formed to be in contact with one side of the second layer. At this time, each of the first and second undoped GaInAs layers must be formed as a graded layer in which the In composition ratio is gradually varied such that the In composition ratio is high on the channel layer side and is low on the buffer layer side and the cap layer side. If the first and second layers and the channel layer are uniform layers each having a constant In composition ratio, a total film thickness of the three layers constituted by the first layer, the channel layer, and the second layer must be smaller than a critical film thickness at which dislocation is caused by lattice distortion. In either case, a region in which carrier electrons are present is not entirely located on the channel layer, but a part of the region extends to the undoped GaInAs layers. For this reason, carrier electrons present in the undoped GaInAs layers are not scattered by dopant atoms, and the carrier electrons are permitted to move at high speed, thereby decreasing the source resistance and increasing the transconductance (gm). In addition, a high-speed operation with low noise can be achieved.

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