Field effect transistor and fabrication process thereof

Details Field effect transistor and fabrication process thereof Field effect transistor and fabrication process thereof

H - Electricity

01

L

H01L 29/772 (2006.01) H01L 21/285 (2006.01) H01L 21/306 (2006.01) H01L 21/335 (2006.01)

Patent

CA 2219598

Using a mask opening a gate region, an undoped GaAs layer is selectively etched with respect to an undoped Al0.2Ga0.8As layer by dry etching with introducing a mixture gas of a chloride gas containing only chlorine and a fluoride gas containing only fluorine (e.g. BCl3 + SF6 or so forth). By about 100% over-etching is performed for the undoped GaAs layer, etching (side etching) propagates in transverse direction of the undoped GaAs layer. With using the mask, a gate electrode of WSi is formed. Thus, a gap in a width of about 20 nm is formed by etching in the transverse direction on the drain side of the gate electrode. By this, a hetero junction FET having reduced fluctuation of characteristics of an FET, such as a threshold value, lower a rising voltage and higher breakdown characteristics.

€ l'aide d'un masque définissant une région de grille, une couche de GaAs non dopée est gravée sélectivement à sec par rapport à une couche Al0.2Ga0.8As non dopée par l'introduction d'un mélange gazeux de chlorure et de fluorure (par ex. BCl3 + SF6, etc.). En effectuant une gravure à 100% environ dans la couche de GaAs non dopée, on obtient une propagation transversale de la gravure dans cette couche. € l'aide du masque, on obtient une électrode de grille de WSi. Un espacement d'environ 20 nm est formée par la gravure dans le sens transversal sur le côté drain de l'électrode de grille. On obtient ainsi un FET à hétérojonction avec une réduction des fluctuations de ses caractéristiques telles que ses tensions de seuil, de montée et de claquage.

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