Field effect transistor and method for manufacturing the same

H - Electricity – 01 – L

Patent

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Details

H01L 29/812 (2006.01) H01L 21/337 (2006.01) H01L 29/10 (2006.01) H01L 29/80 (2006.01)

Patent

CA 2073826

Abstract of the Disclosure A field effect transistor has a gate electrode 15, a source electrode and a drain electrode 15 formed on a GaInAs/GaAs quantum well layer comprising a stock of an undoped GaAs layer, an impurity doped GaInAs layer 3 and an undoped GaAs cap layer, has low resistivity regions 11 formed by ion-implantation in a source regions and the drain regions of the GaInAs/GaAs quantum well layer, has the impurity doped GaInAs layer as a channel, and has a thickness of the undoped GaAs cap layer of 30-50nm. An annealing temperature for activating the low resistivity region 11 is no higher than a temperature at which the GaInAs/GaAs quantum well is not substantially broken and no lower than a temperature at which a sheet resistivity of the low resistivity region 11 is sufficiently reduced. The FET thus manufactured has desired functions of the GaInAs/GaAs quantum well and the low resistivity region 11 and attains a low noise and high speed operation.

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