Field effect transistor with self-aligned gate

Details Field effect transistor with self-aligned gate Field effect transistor with self-aligned gate

H - Electricity

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H01L 21/44 (2006.01) H01L 21/28 (2006.01) H01L 21/336 (2006.01) H01L 21/762 (2006.01) H01L 23/522 (2006.01) H01L 27/108 (2006.01) H01L 29/06 (2006.01) H01L 29/423 (2006.01) H01L 29/49 (2006.01) H01L 29/78 (2006.01)

Patent

CA 1082371

FIELD EFFECT TRANSISTOR WITH SELF-ALIGNED GATE Abstract of the Disclosure A field effect transistor (FET) with a unique gate structure is disclosed wherein the polycrystalline sili- con (polysilicon) gate is self-aligned on its ends with respect to the conductive source and drain regions, and is self aligned on its sides with respect to the non-con- ductive field isolation regions. The boundaries of these conductive and nonconductive regions determine the bound- aries of the channel region of the FET. This double self- alignment feature results in a polysilicon gate, the lateral dimensions and location of which correlate directly with the lateral dimensions and location of the channel region of the FET. The unique gate fabrication technique employed according to the present invention comprises delineating lithographic patterns twice in the same polysilicon layer using the same oxidation barrier masking layer; whereby the first lithographic pattern delineates the FET device regions, and the next lithographic pattern forms the gate regions wherever the two patterns cross each other (i.e., wherever they delineate a common area).

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