Fifo buffer controller

Details Fifo buffer controller Fifo buffer controller

G - Physics

11

C

354/237

G11C 5/00 (2006.01) G06F 5/10 (2006.01)

Patent

CA 1286420

FIFO BUFFER CONTROLLER Abstract of the Disclosure A FIFO ( first in first out) control circuit for providing address information to a FIFO memory. Two up counters are used; one to provide the write address and one to provide the read address. A multiplexer selects which addresses (read or write) are used. Two comparators along with a simple logic circuit provide two status output signals; namely full (or not) and empty (or not).

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