Fifo memory system

Details Fifo memory system Fifo memory system

G - Physics

06

F

354/239

G06F 5/06 (2006.01) G06F 5/10 (2006.01)

Patent

CA 1330600

FIFO MEMORY SYSTEM Abstract of the Disclosure The subject invention is a FIFO memory system and method for buffering data between two data busses. The system comprises a RAM memory, write and read pointer registers, an offset generator, a programmable offset register, and a comparator. The write pointer register stores the address of the next data element to be written into the RAM memory, and the read pointer register stores the address of the next data element to be read from the RAM memory. The offset generator compares the contents of the registers, and generates at an output thereof an offset signal representing the amount of memory space occupied. The programmable offset register provides a programmed offset signal. The comparator compares the offset signal and the programmed offset signal, and provides a ready signal when the offset signal is greater than or equal to the programmed offset signal.

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