Finite field multiplier circuit and use thereof in an error...

Details Finite field multiplier circuit and use thereof in an error... Finite field multiplier circuit and use thereof in an error...

G - Physics

06

F

G06F 7/72 (2006.01) H03M 13/15 (2006.01)

Patent

CA 2244975

Multiplications on a finite field of cardinal 2?m¿ may be achieved by means of a multiplier circuit including j shift registers (R¿0?, ..., R¿j-1?) into which dual-base co-ordinates of one operand are initially loaded, j being an integer greater than 1 divisor of m. The other operand is expressed in standard base. The shift registers are linked to combinatorial logics arranged to deliver the dual-base co-ordinates of the product of the two operands in m/j clock cycles, with j co-ordinates being delivered in each cycle. Multiplication execution rates may thus be increased relative to previously known dual-base multipliers that required at least m clock cycles per operation. The multiplier circuit is particularly useful in BCH decoders.

Pour réaliser des multiplications sur un corps de Galois de cardinal 2m, le circuit multiplieur comprend j registres à décalage (R0, ..., Rj-1) dans lesquels sont initialement chargées les coordonnées en base duale de l'un des opérandes, j étant un entier plus grand que 1 diviseur de m. L'autre opérande est exprimé en base standard. Les registres à décalage sont associés à des logiques combinatoires agencées pour délivrer les coordonnées en base duale du produit des deux opérandes en m/j cycles d'horloge, j coordonnées étant délivrées lors de chaque cycle. On augmente ainsi les cadences d'exécution des multiplications par rapport aux multiplieurs en base duale antérieurement connus qui nécessitaient au moins m cycles d'horloge par opération. Le circuit multiplieur trouve notamment des applications dans des décodeurs BCH.

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