Firmware/hardware system for testing interface logic of a...

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G06F 11/22 (2006.01) G06F 11/267 (2006.01) G06F 11/277 (2006.01) G06F 11/00 (2006.01) G06F 11/10 (2006.01) G06F 11/26 (2006.01)

Patent

CA 1118528

FIREWARE/HARDWARE SYSTEM FOR TESTING INTERFACE LOGIC OF A DATA PROCESSING SYSTEM ABSTRACT OF THE DISCLOSURE A firmware/hardware method and system is provided for testing interface logic in a data processing system having a plurality of system units intercommunicating over a common electrical bus. Under firmware control, an incorrect parity is generated in a main memory address to be loaded into output register of a system unit supplying information to the bus. A bus cycle request is issued by the system unit, and when the bus is made available the system unit acknowledges the memory address to initiate a transfer of data from the bus into the input registers of the system unit. Thereafter, the data in the output registers of the device may be compared with the data in the input registers to detect interface logic errors.

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