G - Physics – 11 – C
Patent
G - Physics
11
C
354/241
G11C 19/00 (2006.01) G06F 5/08 (2006.01) G11C 21/00 (2006.01)
Patent
CA 1038966
Abstract of the Disclosure A first-in/first-out memory device has a shift register with a storage capacity of n stages in which data units can be stored, and a modulo-n address counter having one state repre- senting each stage of the shift register. In one embodiment designed for fast data storage, a data unit is transferred to the input of a shift register during a write mode and the state of the address counter is advanced for each data unit so trans- ferred; during a read mode, data units are recirculated from the output of the shift register to its input, the shift register is shifted n times, the state of the address counter is advanced n - 1 times, and the data unit appearing at the output of the shift register when the address counter state represents an empty shift register is retrieved. In another embodiment designed for fast data retrieval, a data unit is retrieved from the output of a shift register during a read mode and the state of the address counter is advanced for each data unit so transferred; during a write mode, data units are recirculated from the output of the shift register to its input, the shift register is shifted n times, the state of the address counter is advanced n - 1 times, and a data unit is stored in the input of the shift register when the address counter state represents a full shift register.
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