Flexible buffering scheme for multi-rate simd processor

Details Flexible buffering scheme for multi-rate simd processor Flexible buffering scheme for multi-rate simd processor

G - Physics

06

F

G06F 15/00 (2006.01)

Patent

CA 2404020

A single instruction, multiple data (SIMD) architecture for controlling the processing of plurality of data streams (20) in a digital subscriber line (DSL) system has a memory for storing the data channels, a processor (15) operatively coupled with the memory (20) for processing data from the data streams, and a controller (12) for controlling the processor. Storing the data in the memory de-couples the operating rate of the processor (15) and the operating rate of the data streams (20).

L'invention concerne une architecture SIMD (instruction unique, données multiples) permettant de contrôler le traitement d'une pluralité de flots de données (20) dans un système DSL (ligne d'abonné numérique). Cette architecture SIMD comprend une mémoire permettant de stocker des données provenant des canaux, un processeur (15) couplé de manière fonctionnelle à cette mémoire (20) afin de traiter les données des flots de données et un contrôleur (12) permettant de contrôler le processeur. Le stockage des données dans la mémoire permet de découpler la vitesse de fonctionnement du processeur (15) et la vitesse de fonctionnement des flots de données (20).

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