Flexible buffering scheme for multi-rate simd processor

Details Flexible buffering scheme for multi-rate simd processor Flexible buffering scheme for multi-rate simd processor

G - Physics

06

F

G06F 9/50 (2006.01) G06F 15/80 (2006.01) H04L 29/06 (2006.01)

Patent

CA 2303604

There is provided a Single Instruction Multi Data (SIMD) architecture for controlling the processing of plurality of data streams. The SIMD architecture comprises a memory for storing the data from the channels, a processor operatively coupled with the memory for processing data from the data streams, and a controller for controlling the processor. Storing the data in the memory de-couples the operating rate of the processor and the operating rate of the data streams.

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