Floating point data processor

Details Floating point data processor Floating point data processor

G - Physics

06

F

354/239

G06F 7/38 (2006.01)

Patent

CA 1109163

ABSTRACT A digital data processor includes a plurality of memory registers, a floating point adder and a floating point multiplier inter- coupled by a plurality of simultaneously operable parallel buses facilitating multiple parallel operations during one clock cycle or instruction. The floating adder and multiplier each include a number of stages separated by intermediate temporary storage registers which receive the partial results of a computation for use by the next stage during the next clock period. Floating point additions, multiplications and other arithmetic and logical results are produced during each clock cycle.

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