Floating point microprocessor system

Details Floating point microprocessor system Floating point microprocessor system

G - Physics

06

F

354/149

G06F 7/556 (2006.01) G06F 7/00 (2006.01) G06F 7/38 (2006.01)

Patent

CA 1203023

ABSTRACT OF THE DISCLOSURE A microprocessor integrated circuit includes a control, timing and interface section connected by control signal lines to each of the other functional elements. The section is further connected to a 16-bit wide internal information bus by a second bus. A third bus connects the section to a 16-bit wide external information bus. A buffer circuit connects the external informa- tion bus to the internal information bus. The internal informa- tion bus is connected by a fourth bus to a programmable shifter and unpacker section which is connected to a mantissa processor by a 64-bit wide fifth bus and by two 32-bit wide buses. The shifter is connected to an exponent processor by 16-bit wide buses. The mantissa processor is also connected to the internal information bus by a bus. The sign logic circuits are connected to the programmable shifter and unpacker section by a line. The mantissa processor includes a 32-bit arithmetic and logic unit (ALU), a variable width register file, working registers and flip- flops, control PLAs, detection logic and bus buffers. The exponent and sign processor includes a 16-bit wide ALU, variable width register file, working registers control and constants PLAs, detec- tion logic and sign logic and flipflops. The programmable shifter and unpacker is a 64-bit wide shifter capable of shifting in one machine cycle from 0 to 8 positions to the left or 0 to 24 positions to the right. The control, timing and interface section is based on a two-level microprogramming scheme to save microcode and to optimize execution times on a dynamic microcycle.

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