Floating point unit interface

Details Floating point unit interface Floating point unit interface

G - Physics

06

F

354/166

G06F 15/31 (1985.01)

Patent

CA 1274318

ABSTRACT OF THE INVENTION A data processing system which includes a floating point computation unit (FPU) which interfaces with a central processing unit (CPU) in which the CPU supplies a dispatch control signal to inform the FPU that it is about to execute a floating point macroinstruction and supplies a dispatch address which includes the starting address of the floating point microinstructions therefor during the same operating cycle that the dispatch control signal is supplied. A buffer memory is provided in the FPU to store the starting address of one decoded macroinstruction while a sequence of microinstructions for a previously decoded macroinstruction is being executed by the FPU. When the buffer already has a starting address resident in its buffer the FPU supplies a control signal to prevent the CPU from supplying a further dispatch address until the buffer is empty. Other control signals for synchronizing the CPU and FPU operations and data transfers are also provided.

551446

Affiliated with

Also associated with

Rating

Floating point unit interface does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Floating point unit interface, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Floating point unit interface will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1289655