Folded bit line - shared sense amplifiers

Details Folded bit line - shared sense amplifiers Folded bit line - shared sense amplifiers

G - Physics

11

C

352/40

G11C 13/00 (2006.01) G11C 11/34 (2006.01) G11C 11/409 (2006.01) G11C 11/4091 (2006.01) G11C 11/4097 (2006.01)

Patent

CA 1175939

FOLDED BIT LINE - SHARED SENSE AMPLIFIERS ABSTRACT OF THE DISCLOSURE A folded bit line-shared sense amplifier arrangement is described for sensing the logic state of an accessed memory cell in a dynamic MOS random access memory. In the preferred embodiment, a shared sense amplifier is positioned between and coupled to first and second bit lines via first and second isolation transis- tors. The same shared sense amplifier is also positioned between and coupled to third and fourth bit lines via third and fourth isolation transistors. When the state of an accessed memory cell is to be sensed, its memory cell capacitor is coupled to a selected bit line and a dummy cell capacitor is coupled to the bit line adjacent the selected bit line. A decoding circuit selectively activates the shared sense amplifier to sense a difference in voltage between the selected bit line and its adjacent bit line so as to determine the logic state associated with the accessed memory cell. Then, the sense amplifier latches into this logic state for reading by the input/ output buss lines. After the logic state is read, the selecting circuit enables the memory cell capacitor to be refreshed for further sensing by the sense amplifier.

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