Formation of self-aligned stacked cmos structures by lift-off

Details Formation of self-aligned stacked cmos structures by lift-off Formation of self-aligned stacked cmos structures by lift-off

H - Electricity

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356/126

H01L 21/82 (2006.01) H01L 21/822 (2006.01) H01L 27/06 (2006.01)

Patent

CA 1252222

Abstract of the Disclosure A process for fabricating a self-aligned three-dimensionally integrated circuit structure having two channel regions responsive to a common gate electrode. A relatively thick lift-off region is formed over and in alignment with the gate electrode. A thick oxide layer is then deposited over the structure so as to form stressed oxide extending from the lift-off layer sidewalls. A selective etch of the stressed oxide follows. The relatively thick oxide covering the lift-off layer is then removed with the etch of the lift-off layer, the lift-off etch acting through the exposed lift-off layer sidewalls. The formation of an upper field effect transistor gate oxide and a conformal deposition of polysilicon for the channel and source/drain regions follows. The conformally deposited polysilicon retains the contour of the recess formed by the lift-off. The gate aligned recess is then filled with a dopant masking material by deposition and etching, which dopant masking material thereafter defines during implant or diffusion an upper field effect transistor channel region self-aligned with the common gate electrode, The characteristics of the upper field effect transistor can be improved by applying laser recrystallization techniques.

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