Forming interconnections for multilevel interconnection...

Details Forming interconnections for multilevel interconnection... Forming interconnections for multilevel interconnection...

H - Electricity

05

K

356/12, 356/172

H05K 1/11 (2006.01) H01L 21/3213 (2006.01) H01L 21/768 (2006.01) H01L 23/522 (2006.01) H05K 3/46 (2006.01)

Patent

CA 1120611

Abstract A method for forming feedthrough connections, or via studs, between levels of metallization which are typically formed atop semiconductor substrates. A conductive pattern is formed which includes the first level metallurgy, an etch barrier and the feedthrough metallurgy in the desired first level metallurgical configuration. She via stud metal- lurgy alone is then patterned, preferably by reac- tive ion etching, using the etch barrier to prevent etching of the first level metallurgy. An insulator is then deposited around the via studs to form a planar layer of studs and insulator, after which a second level of metallization may be deposited.

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