Four transistor static bipolar memory cell using merged...

Details Four transistor static bipolar memory cell using merged... Four transistor static bipolar memory cell using merged...

G - Physics

11

C

352/82.1

G11C 11/40 (2006.01) G11C 11/411 (2006.01) G11C 11/416 (2006.01) H01L 27/102 (2006.01)

Patent

CA 1121512

ABSTRACT "Four transistor static bipolar memory cell using merged transistors." A bipolar memory cell of reduced size requires only four I2L operated transistors and three access lines. Two current injection transis- tors supply operating current to two inversely operated flip-flop transistors and also function as load devices as well as coupling devices. The three access lines conduct power to the cells as well as the signals for the write and read operation. A write operation is performed by ratioing the currents supplied to a memory cell array such that only a selected cell is written.

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