Four transistor static ram cell

Details Four transistor static ram cell Four transistor static ram cell

G - Physics

11

C

356/23, 352/81

G11C 11/40 (2006.01) G11C 11/403 (2006.01) G11C 11/412 (2006.01) G11C 11/418 (2006.01) G11C 11/419 (2006.01)

Patent

CA 2012668

A static RAM cell includes a first pair of transistors, which act as pass or switching transistors during a read or write operation, and as leads during a refresh operation, and a second pair of current sink transistors connected as a cross-coupled flip-flop and connected to the first pair of transistors. The operation of the memory cell transistors during read and write and refresh operations is controlled by different levels of a control signal applied to their respective control terminals, whereby refreshing does not affect reading or writing of data from or into the SRAM cell.

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